The present invention relates to logic circuits. More particularly, the present invention relates to logic circuits having linear and cellular gate transistors.
The use of complementary metal oxide silicone (MOS) transistors to perform logic functions in digital systems is common. Such logic circuits commonly require two or more inverters connected in series. For example, buffer circuits, oscillator circuits, digital circuits, memory circuits, and other logic circuits require two or more serial inverters. More complex logic circuits also use two or more inverters connected in series, but further expand the circuit to combine inverters in a partially series, partially parallel structure.
Inverters typically include a P-channel type MOS transistor (PMOS) and an N-channel type MOS transistor (NMOS). The design of the transistor can have an effect of the time delay of the logic circuit, the area or size of the circuit, and the current drive required by the circuit. The commercial success of many electronic consumer devices having such logic circuits can be dependent on, among other factors, the size, speed, and battery usage rate of the device.
Accordingly, there is a continuing need for logic circuits that are useful to reduce the size of the circuit, reduce the current drive required by the circuit, and/or increase the speed of the circuit as compared to the prior art logic circuits.